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december 2010 ? 2002 fairchild semiconductor corporation www.fairchildsemi.com nc7sv57 ? nc7sv58 ? rev. 1.0.4 nc7sv57 / nc7sv58 ? tinylogic ? ulp-a universal configur ation two-input logic gates nc7sv57 / nc7sv58 tinylogic ? ulp-a universal configurable two-input logic gates features ? 0.9v to 3.6v v cc supply operation ? 3.6v over-voltage tolerant i/os at v cc from 0.9v to 3.6v ? extremely high speed t pd - 2.5ns: typical for 2.7v to 3.6v v cc - 3.1ns: typical for 2.3v to 2.7v v cc - 4.0ns: typical for 1.65v to 1.95v v cc - 6.0ns: typical for 1.4v to 1.6v v cc - 8.0ns: typical for 1.1v to 1.3v v cc - 23.0ns: typical for 0.9v v cc ? power-off high-impedance inputs and outputs ? high static drive (i oh /i ol ) - 24ma at 3.00v v cc - 18ma at 2.30v v cc - 6ma at 1.65v v cc - 4ma at 1.4v v cc - 2ma at 1.1v v cc - 0.1ma at 0.9v v cc ? proprietary quiet series? noise/emi reduction ? ultra-small micropak? package ? ultra-low dynamic power description the nc7sv57 and nc7sv58 are universal configurable two-input logic gates from fairchild?s ultra-low power (ulp-a) series of tinylogic ? . ulp-a is ideal for applications that require extreme high-speed, high drive, and low power. this product is designed for a wide low-voltage operating range (0.9v to 3.6v v cc ) and applications that require more drive and speed than the tinylogic ? ulp series, but still offer best-in-class, low-power operation. each device is capable of being configured for 1 of 5 unique two-input logic functions. any possible two-input combinatorial logic function can be implemented, as shown in the function selection table . device functionality is selected by how the device is wired at the board level. figures 1 through 10 illustrate how to connect the nc7sv57 and nc7sv58, respectively, for the desired logic function. all inputs have been implemented with hysteresis. the nc7sv57 and nc7sv58 are uniquely designed for optimized power and speed and are fabricated with an advanced cmos technology to achieve high-speed operation while maintaining low cmos power dissipation. ordering information part number top mark package packing method nc7sv57p6x v57 6-lead sc70, eiaj sc-88a, 1.25mm wide 3000 units on tape & reel nc7sv57l6x h3 6-lead micropak?, 1.0mm wide 5000 units on tape & reel nc7sv57fhx h3 6-lead, micropak 2?, 1x1mm body, .35mm pitch nc7sv58p6x v58 6-lead sc70, eiaj sc-88a, 1.25mm wide 3000 units on tape & reel nc7sv58l6x h4 6-lead micropak?, 1.0mm wide 5000 units on tape & reel nc7sv58fhx h4 6-lead, micropak 2?, 1x1mm body, .35mm pitch
? 2002 fairchild semiconductor corporation www.fairchildsemi.com nc7sv57 ? nc7sv58 ? rev. 1.0.4 2 nc7sv57 / nc7v58 ? tinylogic ? ulp a universal configur ation two-input logic gates battery life figure 1. battery life vs. v cc supply voltage notes: 1. tinylogic ? ulp and ulp-a with up to 50% less power consumpt ion can extend your battery life significantly. battery life = (v battery ?i battery ?.9)/(p device )/24hrs/day where p device = (i cc ? v cc ) + (c pd + c l ) ? v cc 2 ? f. 2. assumes ideal 3.6v lithium ion battery with curr ent rating of 900mah and derated 90% and device frequency at 10mhz, with c l = 15pf load.
? 2002 fairchild semiconductor corporation www.fairchildsemi.com nc7sv57 ? nc7sv58 ? rev. 1.0.4 3 nc7sv57 / nc7v58 ? tinylogic ? ulp a universal configur ation two-input logic gates pin configurations figure 2. sc70 (top view) figure 3. micropak? (top through view) figure 4. pin 1 orientation notes: 3. aaa represents product code top mark ( see ordering information ). 4. orientation of top mark determines pin one location. 5. reading the top mark left to right, pin one is the lower left pin. pin definitions pin # sc70 pin # micropak? name description 1 1 i 1 data input 2 2 gnd ground 3 3 i 0 data input 4 4 y output 5 5 v cc supply voltage 6 6 i 2 data input
? 2002 fairchild semiconductor corporation www.fairchildsemi.com nc7sv57 ? nc7sv58 ? rev. 1.0.4 4 nc7sv57 / nc7v58 ? tinylogic ? ulp a universal configur ation two-input logic gates function table inputs nc7sv57 nc7sv58 i 2 i 1 i 0 y = (i 0 ) ? (i 2 ) + (i 1 ) ? (i 2 ) y = (i 0 ) ? (i 2 ) + (i 1 ) ? (i 2 ) l l l h l l l h l h l h l h l l h h l h h l l l h h l h l h h h l h l h h h h l h = high logic level l = low logic level function selection table 2-input logic function device select ion connection configuration 2-input and nc7sv57 figure 5 2-input and with inverted input nc7sv58 figure 11, figure 12 2-input and with both inputs inverted nc7sv57 figure 8 2-input nand nc7sv58 figure 10 2-input nand with inverted input nc7sv57 figure 6, figure 7 2-input nand with both inputs inverted nc7sv58 figure 13 2-input or nc7sv58 figure 13 2-input or with inverted input nc7sv57 figure 6, figure 7 2-input or with both inputs inverted nc7sv58 figure 10 2-input nor nc7sv57 figure 8 2-input nor with inverted input nc7sv58 figure 10, figure 11 2-input nor with both inputs inverted nc7sv57 figure 5 2-input xor nc7sv58 figure 14 2-input xnor nc7sv57 figure 9
? 2002 fairchild semiconductor corporation www.fairchildsemi.com nc7sv57 ? nc7sv58 ? rev. 1.0.4 5 nc7sv57 / nc7v58 ? tinylogic ? ulp a universal configur ation two-input logic gates nc7sv57 logic configurations figure 5 through figure 9 show the logical functions that can be implemented using the nc7sv57. the diagrams show the demorgan?s equivalent logic duals for a given two-input function. the logical implementation is next to the board-level physical implementation of how the pins of the function should be connected. figure 5. 2-input and gate figure 6. 2-input nand gate with inverted a input figure 7. 2-input nand with inverted b input figure 8. 2-input nor gate figure 9. 2-input xnor gate
? 2002 fairchild semiconductor corporation www.fairchildsemi.com nc7sv57 ? nc7sv58 ? rev. 1.0.4 6 nc7sv57 / nc7v58 ? tinylogic ? ulp a universal configur ation two-input logic gates nc7sv58 logic configurations figure 10 through figure 14 show the logical functions that can be implemented using the nc7sv58. the diagrams show the demorgan?s equivalent logic duals for a given two-input function. the logical implementation is next to the board-level physical implementation of how the pins of the function should be connected. figure 10. 2-input nand gate figure 11. 2-input and gate with inverted a input figure 12. 2-input and with inverted b input figure 13. 2-input or gate figure 14. 2-input xor gate
? 2002 fairchild semiconductor corporation www.fairchildsemi.com nc7sv57 ? nc7sv58 ? rev. 1.0.4 7 nc7sv57 / nc7v58 ? tinylogic ? ulp a universal configur ation two-input logic gates absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 4.6 v v in dc input voltage -0.5 4.6 v v out dc output voltage high or low state (6) -0.5 v cc + 0.5 v v cc =0v -0.5 4.6 i ik dc input diode current v in < 0v 50 ma i ok dc output diode current v out < 0v -50 ma v out > v cc +50 i oh / i ol dc output source / sink current 50 ma i cc or i gnd dc v cc or ground current per supply pin 50 ma t stg storage temperature range -65 +150 c p d power dissipation at +85c micropak?-6 130 mw sc70-6 150 micropak2?-6 120 esd human body model, jedec:jesd22-a114 4000 v charged device model, jedec:jesd22-c101 2000 note: 6. io absolute maximum rating must be observed. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. max. unit v cc supply voltage operating 0.9 3.6 v v in input voltage 0 3.6 v v out output voltage v cc =0v 0 3.6 v high or low state 0 v cc i oh /i ol output current v cc =3.0v to 3.6v 24.0 ma v cc =2.3v to 2.7v 18.0 v cc =1.65v to 1.95v 6.0 v cc =1.4v to 1.6v 4.0 v cc =1.1v to 1.3v 2.0 v cc =0.9v 0.1 a t a operating temperature, free air -40 +85 c t/ v minimum input edge rate v in =0.8v to 2.0, v cc =3.0v 10 ns/v ja thermal resistance sc70-6 425 c/w micropak?-6 500 micropak2?-6 560 note: 7. unused inputs must be held high or low. they may not float.
? 2002 fairchild semiconductor corporation www.fairchildsemi.com nc7sv57 ? nc7sv58 ? rev. 1.0.4 8 nc7sv57 / nc7v58 ? tinylogic ? ulp a universal configur ation two-input logic gates dc electrical characteristics symbol parameter v cc conditions t a =25c t a =-40 to 85c units min. max. min. max. v p positive threshold voltage 0.90 0.30 0.70 0.30 0.70 v 1.10 0.40 1.00 0.40 1.00 1.40 0.50 1.40 0.50 1.40 1.65 0.70 1.50 0.70 1.50 2.30 1.00 1.80 1.00 1.80 2.70 1.30 2.20 1.30 2.20 v n negative threshold voltage 0.90 0.10 0.60 0.10 0.60 v 1.10 0.15 0.70 0.15 0.70 1.40 0.20 0.80 0.20 0.80 1.65 0.25 0.90 0.25 0.90 2.30 0.40 1.15 0.40 1.15 2.70 0.60 1.50 0.60 1.50 v h hysteresis voltage 0.90 0.07 0.50 0.07 0.50 v 1.10 0.08 0.60 0.08 0.60 1.40 0.10 0.80 0.10 0.80 1.65 0.15 1.00 0.15 1.00 2.30 0.25 1.10 0.25 1.10 2.70 0.40 1.20 0.40 1.20 v oh high level output voltage 0.90 i oh =-100a v cc -0.1 v cc -0.1 v 1.10 v cc 1.30 v cc -0.1 v cc -0.1 1.40 v cc 1.60 v cc -0.2 v cc -0.2 1.65 v cc ? 1.95 v cc -0.2 v cc -0.2 2.30 v cc 2.70 v cc -0.2 v cc -0.2 2.70 v cc 3.60 v cc -0.2 v cc -0.2 1.10 v cc 1.30 i oh =-2ma .75 x v cc .75 x v cc 1.40 v cc 1.60 i oh =-4ma .75 x v cc .75 x v cc 1.65 v cc 1.95 i oh =-6ma 1.25 1.25 2.30 v cc 2.70 2.0 2.0 2.30 v cc 2.70 i oh =-12ma 1.8 1.8 2.70 v cc 3.60 2.2 2.2 2.30 v cc 2.70 i oh =-18ma 1.7 1.7 2.70 v cc 3.60 2.4 2.4 2.70 v cc 3.60 i oh =-24ma 2.2 2.2 continued on following page?.
? 2002 fairchild semiconductor corporation www.fairchildsemi.com nc7sv57 ? nc7sv58 ? rev. 1.0.4 9 nc7sv57 / nc7v58 ? tinylogic ? ulp a universal configur ation two-input logic gates dc electrical characteristics (continued) symbol parameter v cc conditions t a =25c t a =-40 to 85c units min. max. min. max. v ol low level output voltage 0.90 i ol =100a 0.1 0.1 v 1.10 v cc 1.30 0.1 0.1 1.40 v cc 1.60 0.2 0.2 1.65 v cc ? 1.95 0.2 0.2 2.30 v cc 2.70 0.2 0.2 2.70 v cc ? 3.60 0.2 0.2 1.10 v cc 1.30 i ol =2ma .25 x v cc .25 x v cc 1.40 v cc 1.60 i ol =4ma .25 x v cc .25 x v cc 1.65 v cc 1.95 i ol =6ma 0.3 0.3 2.30 v cc 2.70 i ol =12ma 0.4 0.4 2.70 v cc 3.60 0.4 0.4 2.30 v cc 2.70 i ol =18ma 0.6 0.6 2.70 v cc 3.60 0.4 0.4 2.70 v cc 3.60 i ol =24ma 0.55 0.55 i in input leakage current 0.90 to 3.60 0 v in 3.6v 0.1 0.5 a i off power off leakage current 0 0 (v in, v o ) 3.60 0.5 0.5 a i cc quiescent supply current 0.90 to 3.60 v in =v cc or gnd 0.9 0.9 a v cc v in 3.6v 0.9 ac electrical characteristics symbol parameter v cc conditions t a =25c t a =-40 to 85c units figure min. typ. min. typ. min. t phl , t plh propagation delay 0.90 c l =15pf, r l =1m 15.0 ns figure 15 figure 16 1.10 v cc 1.30 c l =15pf, r l =2k 4.0 8.0 16.5 3.3 31.0 1.40 v cc 1.60 2.0 6.0 10.0 2.0 12.0 1.65 v cc 1.95 c l =30pf, r l =500 2.0 4.0 9.1 1.9 10.0 2.30 v cc 2.70 1.5 3.1 6.2 1.4 6.7 2.70 v cc 3.60 1.2 2.5 5.4 1.2 6.1 c in input capacitance 0 8 pf c out output capacitance 0 12 pf c pd power dissipation capacitance 0.90 to 3.60 v i =0v or v cc , f=10mhz 10 pf
? 2002 fairchild semiconductor corporation www.fairchildsemi.com nc7sv57 ? nc7sv58 ? rev. 1.0.4 10 nc7sv57 / nc7v58 ? tinylogic ? ulp a universal configur ation two-input logic gates ac loadings and waveforms figure 15. ac test circuit figure 16. ac waveforms symbol v cc 3.3v 0.3v 2.5v 0.2v 1.8v 0.15v 1.5v 0.10v 1.2v 0.10v 0.9v v mi 1.5v v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v mo 1.5v v cc /2 v cc /2 v cc /2 v cc /2 v cc /2
? 2002 fairchild semiconductor corporation www.fairchildsemi.com nc7sv57 ? nc7sv58 ? rev. 1.0.4 11 nc7sv57 / nc7v58 ? tinylogic ? ulp a universal configur ation two-input logic gates physical dimensions detail a scale: 60x b 1.90 2.00 0.20 0.50 min 1.00 0.80 1.10 0.80 0.10 c 0.25 0.10 0.46 0.26 0.20 gage plane (r0.10) 30 0 seating plane c 0.10 0.00 notes: unless otherwise specified a) this package conforms to eiaj sc-88, 1996. b) all dimensions are in millimeters. c) dimensions do not include burrs or mold flash. d) drawing filename: mkt-maa06arev6 2.100.30 0.10 ab 0.65 1.30 (0.25) 0.30 0.15 1 1.25 0.10 3 1.30 0.40 min see detail a land pattern recommendation 6 a 4 c 0.65 l symm pin one figure 17. 6-lead, sc70, eiaj sc-88a, 1.25mm wide package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf package designator tape section cavity number cavity status cover type status p6x leader (start end) 125 (typical) empty sealed carrier 3000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2002 fairchild semiconductor corporation www.fairchildsemi.com nc7sv57 ? nc7sv58 ? rev. 1.0.4 12 nc7sv57 / nc7v58 ? tinylogic ? ulp a universal configur ation two-input logic gates physical dimensions 2. dimensions are in millimeters 1. conforms to jedec standard m0-252 variation uaad 4. filename and revision: mac06arev4 notes: 3. drawing conforms to asme y14.5m-1994 top view recommened land pattern bottom view 1.45 1.00 a b 0.05 c 0.05 c 2x 2x 0.55max 0.05 c (0.49) (1) (0.75) (0.52) (0.30) 6x 1x 6x pin 1 detail a 0.075 x 45 chamfer 0.25 0.15 0.35 0.25 0.40 0.30 0.5 (0.05) 1.0 5x detail a pin 1 terminal 0.40 0.30 0.45 0.35 0.10 0.00 0.10 cba 0.05 c c 0.05 c 0.05 0.00 5x 5x 6x (0.13) 4x 6x pin 1 identifier (0.254) 5. pin one identifier is 2x length of any 5 other line in the mark code layout. figure 18. 6-lead, micropak?, 1.0mm wide package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf . package designator tape section cavity number cavity status cover type status l6x leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2002 fairchild semiconductor corporation www.fairchildsemi.com nc7sv57 ? nc7sv58 ? rev. 1.0.4 13 nc7sv57 / nc7v58 ? tinylogic ? ulp a universal configur ation two-input logic gates physical dimensions 1.00 b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994 notes: a. complies to jedec mo-252 standard 0.05 c a b 0.55max 0.05 c c 0.35 0.09 0.19 123 0.35 0.25 5x 6x detail a 0.60 (0.08) 4x (0.05) 6x 0.40 0.30 0.075x45 chamfer 5x 0.40 0.35 1x 0.45 6x 0.19 top view bottom view 0.66 0.10 cba .05 c 0.89 pin 1 0.05 c 2x 2x 1.00 d. landpattern recommendation is based on fsc e. drawing filename and revision: mgf06arev3 0.52 0.73 0.57 0.20 6x 1x 5x recommended land pattern for space constrained pcb detail a pin 1 lead scale: 2x alternative land pattern for universal application design. 0.90 min 250um 65 4 0.35 (0.08) 4x side view figure 19. 6-lead, micropak2, 1x1mm body, .35mm pitch package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/micropak2_6l_tr.pdf . package designator tape section cavity number cavity status cover type status fhx leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2002 fairchild semiconductor corporation www.fairchildsemi.com nc7sv57 ? nc7sv58 ? rev. 1.0.4 14 nc7sv57 / nc7v58 ? tinylogic ? ulp a universal configur ation two-input logic gates

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